Ultra-Low Voltage Nano-Scale Memories

Preface

Table of Contents

An Introduction to LSI Design

1.1. Introduction

1.2. Basics of LSI Devices

1.3. Leakage Currents

1.3.1. Subthreshold Current

1.3.2. Gate-Tunneling Current

1.3.3. Substrate Current

1.3.4. pn-Junction Current

1.4. Basics of CMOS Digital Circuits

1.4.1. CMOS Inverter

1.4.2. NOR and NAND Gates

1.4.3. Cross-Coupled CMOS Sense Amplifier

1.4.4. Level Shifter

1.4.5. Charge Pump

1.4.6. Ring Oscillator

1.5. Basics of CMOS Analog Circuit

1.6. Basics of Memory LSIs

1.6.1. Memory Chip Architectures

1.6.2. Memory Cells

1.7. Basics of DRAMs

1.7.1. Read Operation

1.7.2. Write Operation

1.7.3. Refresh Operation

1.8. Basics of SRAMs

1.8.1. Read Operation

1.8.2. Write Operation

1.9. Basics of Flash Memories

1.10. Soft Errors

1.11. Redundancy Techniques

1.12. Error Checking and Correcting (ECC) Circuit

1.13. Scaling Laws

1.13.1. Constant Electric-Field Scaling

1.13.2. Constant Operation-Voltage Scaling

1.13.3. Combined Scaling

1.14. Power Supply Schemes

1.15. Trends in Power Supply Voltages

1.16. Power Management for Future Memories

1.16.1. Static Control of Internal Supply Voltages

1.16.2. Dynamic Control of Internal Supply Voltages

1.17. Roles of On-Chip Voltage Converters

References

Ultra-Low Voltage Nano-Scale DRAM Cells

2.1. Introduction

2.2. Trends in DRAM-Cell Developments

2.2.1. The 1-T Cell and Related Cells

2.2.2. Gain Cells

2.3. 1-T-Based Cells

2.3.1. The Data-Line Arrangement

2.3.2. The Data-Line Precharging Scheme

2.4. Design of the Folded-Data-Line 1-T Cell

2.5. Design of the Open-Data-Line 1-T Cell

2.5.1. Noise-Generation Mechanism

2.5.2. Concepts for Noise Reduction

2.5.3. Data-Line Shielding Circuits

2.6. Design of the 2-T Cell

2.7. Design of Double-Gate Fully-Depleted SOI Cells

References

Ultra-Low Voltage Nano-Scale SRAM Cells

3.1. Introduction

3.2. Trends in SRAM-Cell Developments

3.3. Leakage Currents in the 6-T SRAM Cell

3.4. The Voltage Margin of the 6-T SRAM Cell

3.4.1. Read and Write Voltage Margin

3.4.2. Signal Charge

3.5. Improvements of the Voltage Margin of the 6-T SRAM Cell

3.5.1. Lithographically Symmetric Cell Layout

3.5.2. Power-Supply Controlled Cells

3.5.3. Fully-Depleted SOI Cells

3.6. The 6-T SRAM Cell Compared with the 1-T DRAM Cell

Leakage Reduction for Logic Circuits in RAMs

4.1. Introduction

4.2. Basic Concepts for Leakage Reduction of MOSTs

4.3. Basics of Leakage Reduction Circuits

4.4. Gate-Source Reverse Biasing Schemes

4.4.1. Gate-Source Self-Reverse Biasing

4.4.2. Gate-Source Offset Driving

4.5. Applications to RAMs

4.5.1. Leakage Sources in RAMs

4.5.2. Features of Peripheral Circuits of RAMs

4.5.3. Applications to DRAM Peripheral Circuits

4.5.4. Applications to SRAM Peripheral Circuits

References

Variability Issue in the Nanometer Era

5.1. Introduction

5.2. Vt Variation in the Nanometer Era

5.3. Leakage Variations

5.4. Speed Variations of Logic Circuits

5.5. Variations in Vt Mismatch of Flip-Flop Circuits

5.6. Solutions for the Reductions

References

Reference Voltage Generators

6.1. Introduction

6.2. The Vt-Referenced VREF Generator

6.3. The Vt-Difference Vt VREF Generator

6.4. The Bandgap V

6.4. The Bandgap VREF Generator

6.5. The Reference Voltage Converter/Trimming Circuit

6.6. Layout Design of V ref Generator

References

Voltage Down-Converters

7.1. Introduction

7.2. The Series Regulator

7.2.1. DC Characteristics

7.2.2. Transient Characteristics

7.2.3. AC Characteristics and Phase Compensation

7.2.4. PSRR

7.2.5. Low-Power Design

7.2.6. Applications

7.3. The Switching Regulator

7.4. The Switched-Capacitor Regulator

7.5. The Half -VDD Generator

References

Voltage Up-Converters and Negative Voltage Generators

8.1. Introduction

8.2. Basic Voltage Converters with Capacitor

8.3. Dickson-Type Voltage Multiplier

8.4. Switched-Capacitor (SC)-Type Voltage Multipliers

8.5. Comparisons between Dickson-Type and SC- Type Multipliers

8.6. Voltage Converters with an Inductor

8.7. Level Monitor

A8.1. Efficiency Analysis of Voltage Up-Converters A8.1.1. Dickson- Type Charge Pump Circuit

A8.1.2. Switched-Capacitor-Type Charge Pump Circuit

References

High-Voltage Tolerant Circuits

9.1. Introduction

9.2. Needs for High-Voltage Tolerant Circuits

9.3. Concepts of High-Voltage Tolerant Circuits

9.4. Applications to Internal Circuits

9.5. Applications to I/O Circuits

9.5.1. Output Buffers

9.5.2. Input Buffers

References

Index